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參數(shù)資料
| 型號： | IBM13M32734BCD |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 579K |
| 代理商： | IBM13M32734BCD |
IBM13M32734BCD
32M x 72 2-Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 20
19L7143.E93758B
2/99
30
Minimum RAS Pulse width (t
RAS
)
-260, -360
-10
50.0ns
60.0ns
128MB
2.0ns
3.0ns
1.0ns
1.0ns
2.0ns
3.0ns
1.0ns
1.0ns
Undefined
PC100 1.2A
02
Checksum Data
IBM
Toronto, Canada
Vimercate, Italy
ASCII ‘13M32734BC”R”-
260Y’
ASCII ‘13M32734BC”R”-
360Y’
ASCII ‘13M32734BC”R”-
10Y’
“R” plus ASCII blank
Year/Week Code
Serial Number
Undefined
100MHz
66MHz
CLK0, CL=3, ConAP
CL = 2, 3
Undefined
32
3C
20
20
30
10
10
20
30
10
10
00
12
02
cc
31
Module Bank Density
32
Address and Command Setup Time
Before Clock
-260, -360
-10
-260, -360
-10
-260, -360
-10
-260, -360
-10
33
Address and Command Hold Time After
Clock
34
Data Input Setup Time Before Clock
35
Data Input Hold Time After Clock
36 - 61
Reserved
62
SPD Revision
-260, -360
-10
63
Checksum for bytes 0 - 62
Manufacturers’ JEDEC ID Code
3
64 - 71
A400000000000000
91
53
31334D33323733344243rr
2D323630592020
31334D33323733344243rr
2D333630592020
31334D33323733344243rr
2D313059202020
rr20
yyww
ssssssss
Not Specified
64
66
85
06
00
72
Assembly Manufacturing Location
73 - 90
Assembly Part Number
-260
4, 5
-360
-10
91 - 92
93 - 94
95 - 98
99 - 125 Reserved
Assembly Revision Code
Assembly Manufacturing Date
Assembly Serial Number
5
6, 7
8
126
Module Supports this Clock Frequency
-260, -360
-10
-260, -360
-10
127
Attributes for clock frequency defined in
Byte 126
128 - 255 Open for Customer Use
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns (100MHz) for the -260 and -360 and 15ns (66MHz) for the -10.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
Discontinued (8/99 - last order; 12/99 - last ship)
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