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參數(shù)資料
| 型號： | IBM13M16734JCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 One-Bank Registered / Buffered SDRAM Module(16M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 1,600 × 72單銀行注冊/緩沖內(nèi)存模組（16米x 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 531K |
| 代理商： | IBM13M16734JCB |
IBM13M16734JCB
16M x 72 One-Bank Registered / Buffered SDRAM Module
06K7739.H03380
4/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 22
Features
168-Pin Registered 8-Byte Dual In-Line Memory
Module
16Mx72 Synchronous DRAM DIMM
Performance:
Intended for 133MHz applications
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have four internal banks
Module has one physical bank
Fully Synchronous to positive Clock Edge
Programmable Operation:
- DIMM CAS Latency:4 (Registered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page
- Operation: Burst Read and Write
or Multiple Burst Read with Single Write
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
12/10/2 Addressing (Row/Column/Bank)
4096 refresh cycles distributed across 64ms
Card size: 5.25" x 1.5" x 0.157"
Gold contacts
SDRAM
S
in TSOP - Type II Package
Serial Presence Detect with Write protect feature
Description
IBM13M16734JCB is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as a 16Mx72 high-speed memory array.
The DIMM uses nine 16Mx8 SDRAMs in 400 mil
TSOP packages. The DIMM achieves high-speed
data-transfer rates of 133MHz by employing a
prefetch/pipeline hybrid architecture that synchro-
nizes the output data to a system clock.
The DIMM is intended for use in applications oper-
ating at 133MHz memory bus speed. All control and
address signals are re-driven through registers/buff-
ers to the SDRAM devices. Operating in registered
mode (REGE pin tied high), the control/address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the
following rising clock edge (data access is delayed
by one clock).
A phase-lock loop (PLL) on the DIMM is used to re-
drive the clock signals to the SDRAM devices to
minimize system clock loading. (CK0 is connected
to the PLL, and CK1, CK2, and CK3 are terminated
on the DIMM.) A single clock enable (CKE0) con-
trols all devices on the DIMM, enabling the use of
SDRAM power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
be programmed into the DIMM by address inputs
A0-A9, I/O addresses BA0 and BA1 using the mode
register set cycle. The DIMM CAS latency, when
operated in Registered mode, is one clock later than
the device CAS latency due to the address and con-
trol signals being clocked to the SDRAM devices.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufac-
turer. The last 128 bytes are available to the cus-
tomer and may be write protected by providing a
high level to pin 81 on the DIMM. An on-board pull-
down resistor keeps this in the write-enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
-75A Reg.
4
133
7.5
5.65
Units
DIMM CAS Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
MHz
ns
ns
.
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