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參數(shù)資料
| 型號： | IBM13N16644JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 One-Bank Unbuffered SDRAM Module(16M x 64 1組不帶緩沖同步動態(tài)RAM模塊（16M x 64高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 1,600 × 64單銀行無緩沖內(nèi)存模組（16米x 64 1組不帶緩沖同步動態(tài)內(nèi)存模塊（1,600 × 64高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 340K |
| 代理商： | IBM13N16644JCA |
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
06K3912.H01723
1/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 18
Features
168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
Intended for PC100 applications
Clock Frequency: 100MHz
Clock Cycle: 10.0ns
-260 and -360 speed sorts
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have four internal banks
Module has one physical bank
Fully Synchronous to positive Clock Edge
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge commands
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page
(Full-Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Suspend Mode and Power Down Mode
12/10/2 Addressing (Row/Column/Bank)
4096 Refresh cycles distributed across 64ms
Card size: 5.25" x 1.375" x 0.106"
Gold contacts
SDRAMs in TSOP Type II Package
Serial Presence Detect with Write Protect
Description
IBM13N16644JCA / IBM13N16734JCA are unbuf-
fered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
16Mx64 and 16Mx72 high-speed memory arrays
and are configured as one 16M x 64/72 physical
bank. The DIMMs use eight (16Mx64) or nine
(16Mx72) 16Mx8 SDRAMs in 400mil TSOP II pack-
ages. The DIMMs achieve high-speed data transfer
rates of up to 100MHz by employing a prefetch/pipe-
line hybrid architecture that supports the JEDEC 1N
rule while allowing very low burst power.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK2). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0/S2, DQMB, and CKE0 signals. A
command decoder initiates the necessary timings
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and Burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
.
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