參數(shù)資料
型號(hào)： IBM11M8845HB
廠商： IBM Microeletronics
英文描述： 8M x 72 Chipkill Correct DRAM Module(8M x 72 工業(yè)標(biāo)準(zhǔn)的168腳8位動(dòng)態(tài)RAM模塊（帶信號(hào)糾錯(cuò)系統(tǒng)）)
中文描述： 8米× 72 Chipkill正確的內(nèi)存（8米× 72工業(yè)標(biāo)準(zhǔn)的168腳8位動(dòng)態(tài)內(nèi)存模塊（帶信號(hào)糾錯(cuò)系統(tǒng)））
文件頁(yè)數(shù)： 7/29頁(yè)
文件大?。?/td> 512K
代理商： IBM11M8845HB
IBM11M8845HB
8M x 72 Chipkill Correct DRAM Module
01L5840.00
Rev 12/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 29
AC Characteristics
(T
A
= 0 to +65
°
C, V
CC
= 3.3V
±
0.15V)
1. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and
V
IL
.
2. An initial pause of 200ms is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the
DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specification of 50ns or
60ns.
4. AC measurements assume t
T
= 2ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-50
-60
Unit
Notes
Min
Max
Min
Max
t
RC
Random Read or Write Cycle Time
89
—
104
—
ns
t
RP
RAS Precharge Time
35
—
40
—
ns
t
CP
CAS Precharge Time
8
—
10
—
ns
t
RAS
RAS Pulse Width
50
100K
60
100K
ns
t
CAS
CAS Pulse Width
8
100K
10
100K
ns
t
ASR
Row Address Setup Time
5
—
5
—
ns
t
RAH
Row Address Hold Time
8
—
8
—
ns
t
ASC
Column Address Setup Time
2
—
2
—
ns
t
CAH
Column Address Hold Time
7
—
10
—
ns
t
RCD
RAS to CAS Delay Time
12
32
12
40
ns
1
t
RAD
RAS to Column Address Delay Time
10
20
10
25
ns
3
t
RSH
RAS Hold Time
13
—
15
—
ns
t
CSH
CAS Hold Time
43
—
48
—
ns
t
CRP
CAS to RAS Precharge Time
10
—
10
—
ns
t
ODD
OE to D
IN
Delay Time
18
—
20
—
ns
3
t
DZO
OE Delay Time from D
IN
-2
—
-2
—
ns
4
t
DZC
CAS Delay Time from D
IN
-2
—
-2
—
ns
4
t
T
Transition Time (Rise and Fall)
1
30
1
30
ns
1. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
2. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
3. Either t
CDD
or t
ODD
must be satisfied.
4. Either t
DZC
or t
DZO
must be satisfied.
Discontinued (7/00 - last order; 9/00 - last ship)
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