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IBM11N2645H
IBM11N2735H
2M x 64/72 DRAM MODULE
50H7623.E93788
Released 5/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 31
Features
168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual In-line Memory Module
2Mx64, 2Mx72 Extended Data Out Page Mode
DIMM
S
Performance:
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Au contacts
Optimized for byte-write non-parity, or ECC
applications
System Performance Benefits:
-Non buffered for increased performance
-Reduced noise (35 V
SS
/V
CC
pins)
-Byte write, byte read accesses
-Serial PDs
Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
Refresh Modes: RAS-Only, CBR and Hidden
Refresh
2048 refresh cycles distributed across 32ms
11/10 addressing (Row/Column)
Card size: 5.25" x 1.0" x 0.157"
DRAMS in TSOP Package
Description
IBM11N2645H/IBM11N2735H are industry standard
168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as 2Mx64 and 2Mx72
high speed memory arrays designed with EDO
DRAMs for non-parity or ECC applications. The
DIMMs use 8 (x64) or 9 (x72) 2Mx8 EDO DRAMs in
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 20ns (EDO, 50ns sort).
The DIMMs use serial presence detects imple-
mented via a serial EEPROM using the two pin I
2
C
protocol. This communication protocol uses Clock
(SCL) and Data I/O (SDA) lines to synchronously
clock data between the master (system logic) and
the slave EEPROM device (DIMM). The EEPROM
device address pins (SA0-2) are brought out to the
DIMM tabs to allow 8 unique DIMM/EEPROM
addresses. The first 128 bytes are utilized by the
DIMM manufacturer and the second 128 bytes of
serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include the buffered
DIMMs (x64 non- parity and x72 ECC Optmized) for
applications which can benefit from the on-card buff-
ers.
-50
50ns
13ns
25ns
84ns
20ns
-60
60ns
15ns
30ns
104ns
25ns
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
EDO Mode Cycle Time
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
Discontinued (9/98 - last order; 3/99 last ship)