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參數(shù)資料
| 型號(hào)： | IBM11D4480BG |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 36 ECC-on-SIMM（single in-line memory module）(4M x 36 片上帶可兼容的糾錯(cuò)代碼的單列動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4米× 36 ECC的問(wèn)題，上海藥物研究所（單列直插式內(nèi)存模塊）（4米× 36片上帶可兼容的糾錯(cuò)代碼的單列動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | IBM11D4480BG |
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IBM11D4480BG
IBM11E4480BG
4M x 36 ECC-on-SIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 18
26H2527
Revised 10/98
Write Cycle
Symbol
Parameter
-70
Units
Min
Max
t
WCS
Write Command Set Up Time
0
—
ns
t
WCH
Write Command Hold Time
15
—
ns
t
WP
Write Command Pulse Width
15
—
ns
t
RWL
Write Command to RAS Lead Time
20
—
ns
t
CWL
Write Command to CAS Lead Time
20
—
ns
t
DS
D
IN
Setup Time
0
—
ns
t
DH
D
IN
Hold Time
20
—
ns
Read Cycle
Symbol
Parameter
-70
Units
Notes
Min
Max
t
RAC
Access Time from RAS
—
70
ns
1, 2
t
CAC
Access Time from CAS
—
20
ns
1, 2
t
AA
Access Time from Address
—
35
ns
1, 2
t
RCS
Read Command Setup Time
0
—
ns
t
RCH
Read Command Hold Time to CAS
0
—
ns
3
t
RRH
Read Command Hold Time to RAS
0
—
ns
3
t
RAL
Column Address to RAS Lead Time
35
—
ns
t
CAL
Column Address to CAS Lead Time
35
—
ns
t
CLZ
CAS to Output in Low-Z
0
—
ns
t
OH
Output Data Hold Time
0
—
ns
t
CDD
CAS to D
IN
Delay Time
15
—
ns
t
OFF
Output Buffer Turn-off Delay
0
15
ns
4
1. Measured with the specified current load and 100pF.
2. Access time is determined by the latter of t
RAC
, t
CAC
, t
CPA
, t
AA
.
3. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
4. t
OFF
(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
Discontinued (7/00 - last order; 9/00 - last ship)
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