參數(shù)資料
型號(hào)： IBM0436A86SQKA
廠商： IBM Microeletronics
英文描述： 8 Mb Synchronous Communication SRAM(8M位同步流水線式通信靜態(tài)RAM)
中文描述： 8兆同步通信的SRAM（800萬(wàn)位同步流水線式通信靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 4/17頁(yè)
文件大?。?/td> 299K
代理商： IBM0436A86SQKA
IBM0418A86LQKA
IBM0418A86SQKA
8 Mb Synchronous Communication SRAM
IBM0436A86LQKA
IBM0436A86SQKA
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 16
llwp.03
10/11/2000
Pin Descriptions
Symbol
Type
Description
CLK
Input
Clock:
This signal registers the address, data, chip enables, byte write enables and burst control inputs on
its rising edge. All synchronous inputs must meet setup and hold times around clock
’
s rising edge.
CKE
Input
Synchronous Clock Enable:
This active low input enables the CLK input. When high, the CLK input is
ignored, and the previous cycle is extended.
CE
CE2
Input
Synchronous Chip enable:
These active low inputs are used to enable the device and are sampled only
when a new external address is loaded (ADV/LD low). Double cycle deselect protocol.
CE2
Input
Synchronous Chip enable:
This active high input is used to enable the device and is sampled only when
a new external address is loaded (ADV/LD low). Double cycle deselect protocol.
ADV/LD
Input
Synchronous Address Advance/Load:
When low, a new address is loaded into the device (and Burst
counter). When high, the internal burst counter is advanced and used (R/W is ignored).
SA0
SA1
SA
Input
Synchronous Address Inputs.
SA0 and SA1 are the least significant Address bits, and are used to set
the Burst Address counter for Burst operations.
Pin 84 is reserved as the High order Address for the 16 Mb Late-Late-Write SRAM.
BWa
BWb
BWc
Input
Synchronous Byte Writes:
These inputs allow individual bytes to be written (low), or masked (high) dur-
ing a write operation. Byte writes are registered on the same clock edge as the Write Address (whether it is
an externally provided or internally generated Address). These inputs have no effect during a Read opera-
tion.
R/W
Input
Read/Write:
This synchronous input, sampled at the rising edge of CLK when ADV/LD is low, determines
whether a Read (high) or Write (low) operation is initiated. For Write operations, the Byte Write Enable
inputs provide byte control for Partial Write operations.
OE
Input
Output Enable:
This active low, asynchronous input enables the Output Drivers.
MODE(LBO)
Input
Mode:
A low on this pin selects Linear Burst order. A high or NC will default to Interleaved Burst order. Do
not change input state once the device is operating.
DQa
DQb
DQc
DQd
Input/Output
Data I/Os:
DQa is Data Input and Output for Byte
“
a
”
. DQb is for Byte
“
b
”
,DQc is for Byte
“
c
”
and
DQd is for Byte
“
d
”
.
ZZ
Input
Sleep Enable:
This active high, asynchronous input causes the chip to enter Sleep Mode, which is a low
standby-current state. While ZZ is high, all other inputs are ignored, and data in the memory array is
retained. Pin may be left unconnected.
NC
NC
No Connect:
These pins can be left unconnected, or may be connected to GND to minimize thermal
impedance or any other DC input.
V
DD
Supply
Power Supply:
See DC Electrical Characteristicson page 9 and Recommended DC Operating Conditions
on page 8 for range.
V
DDQ
Supply
Isolated Output Buffer Supply
: See DC Electrical Characteristics on page 9 and Recommended DC
Operating Conditions on page 8 for range.
V
SS
Supply
Ground:
GND.
DNU
NC/Input
Do Not Use.
Reserved pins. These can either be left unconnected or wired to GND to improve thermal
impedance.
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