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參數(shù)資料
| 型號： | IBM0436A86LQKA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8 Mb Synchronous Communication SRAM(8M位同步流水線式通訊靜態(tài)RAM) |
| 中文描述： | 8兆同步通信的SRAM（800萬位同步流水線式通訊靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 299K |
| 代理商： | IBM0436A86LQKA |
IBM0418A86LQKA
IBM0418A86SQKA
8 Mb Synchronous Communication SRAM
IBM0436A86LQKA
IBM0436A86SQKA
llwp.03
10/11/2000
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 16
SRAM Features
Late-Late-Write
In the Late-Late-Write QBT (Quick Bus Turn) function, write data must be registered on the N+2 clock cycle
and addresses and controls registered on the N base clock cycle. Read data is available in the N+1 clock
cycle. Read data is valid for a full cycle plus access time from the time the address is registered. Write data
must be provided with set-up time two cycles after the valid address. This provides 100% bus utilization.
In the unique case when a read cycle occurs after a write cycle to the same address, write data information is
stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array
will be updated with the address and data from the holding registers. Read cycle addresses are monitored to
determine if read data is supplied from the SRAM array or from the write buffer holding registers.
Bypassing the SRAM array occurs on a byte-by-byte basis. When only one byte is written during a write
cycle, read data from the address last written will have new byte data from the write buffer and the remaining
bytes from the SRAM array. Late-Late-Write is extremely similar to Late-Write; just one additional cycle is
needed to register the write data.
The IBM0418/36A86 SRAM can operate in either linear or interleave burst modes using the LBO pin.
Addresses are loaded via the ADV/LD pin. Once an address is loaded, it is designated as either a write or
read address from the initial address load. All burst addresses produced by ADV pulses are either read or
write as designated by the initial address. Only read OR write operation within a burst-loaded address is sup-
ported.
Power Down Mode
Power Down Mode, or
“
Sleep Mode,
”
is accomplished by switching asynchronous signal ZZ high. When pow-
ering-down the SRAM inputs must be dropped first and V
DDQ
must be dropped before or simultaneously with
V
DD
.
Power-Up Requirements
In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 50
μ
s of power-up
time after V
DD
reaches its operating range. SRAM power-up requires V
DD
to be powered before or simulta-
neously with V
DDQ
and inputs after V
DDQ
. V
DDQ
should not exceed V
DD
supply by more than 0.4 V during
power-up.
Sleep Mode Operation
Sleep mode is a low-power mode initiated by bringing the asynchronous ZZ pin high. During Sleep mode, all
other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High-Z are
guaranteed after the specified Sleep mode enable time. During Sleep mode, the array data contents are pre-
served. Sleep mode must not be initiated until after all pending operations have completed, as any pending
operation is not guaranteed to properly complete after Sleep mode is initiated. Sense amp data is lost. Nor-
mal operation can be resumed by bringing ZZ low, but only after specified Sleep mode recovery time.
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