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參數(shù)資料
| 型號(hào)： | IBM0418A86LQKA-6 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 STANDARD SRAM, 3.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | IBM0418A86LQKA-6 |
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IBM0418A86LQKA
IBM0436A86LQKA
IBM0418A86SQKA
IBM0436A86SQKA
8 Mb Synchronous Communication SRAM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 16
llwp.03
10/11/2000
Cycle Definition Truth Table
Operation
Address
used
CE
CE2
ZZ
ADV/
LD
R/W
BWx
OE
CKE
CLK
DQ
Notes
Deselect Cycle
None
H
X
L
X
L
→H
High-Z
Deselect Cycle
None
X
H
X
L
X
L
→H
High-Z
Deselect Cycle
None
X
L
X
L
→H
High-Z
Deselect Cycle
(Continue)
None
XXX
L
H
XX
X
L
→H
High-Z
Read Cycle
(Begin Burst)
External
L
H
L
H
X
L
→H
Q
Read Cycle
(Continue Burst)
Next
XXX
L
H
XX
L
→H
Q
No Op /Dummy Read
(Begin Burst)
External
L
H
L
H
X
H
L
→H
High-Z
Dummy Read
(Continue Burst)
Next
XXX
L
H
XXH
L
→H
High-Z
Write Cycle
(Begin Burst)
External
LL
H
L
LLL
X
L
→H
Write Cycle
(Continue Burst)
Next
X
L
H
XL
L
→H
D
No Op /Write Abort
(Begin Burst)
None
LL
H
L
LL
H
X
L
→H
High-Z
Write Abort
(Continue Burst)
Next
XXX
L
H
X
H
X
L
→H
High-Z
Clock Disabled
(Stall)
Current
XXX
L
XXX
X
H
L
→H
Held
Sleep Mode
None
XXXH
XXX
XX
X
High-Z
1. Continue Burst Cycles are initiated with the ADV/LD pin held high. The type of cycle that is performed (Deselect, Read or Write) is
determined by the initial Deselect or Begin Read/Write burst cycle.
2. The address counter is incremented for all Continue Burst cycles (see
ear Burst Sequence Truth Table on page 7 for Burst order and wrap information).
3. Dummy Read and Write Abort cycles can be considered Non-Operations or “NOP.” All BWx inputs must be High to prevent a Write
operation from being performed.
4. OE may be tied low to reduce the number of control pins for the SRAM. The device will automatically tri-state the output drivers
during a Write cycle. By carefully controlling the OE timings, cycle time improvements can be obtained.
5. If a Clock Disable (CKE = High) command is issued during a Read operation, the DQ bus will remain active (Low-Z). If it occurs
during a Write operation, the bus will remain inactive (High-Z), and any pending Data-In is delayed by an additional cycle. No oper-
ation will be performed during the Clock Disable cycle.
X=Don’t Care, H=Logic High, L= Logic Low. BWx=H means all byte write inputs (BWa,BWb,BWc,BWd)are High. BWx=L
means one or more byte write signals are Low. (See
Read/Write Command Truth Table on page 7 for more information on
byte enable control).
All inputs except OE and ZZ must meet setup and hold times around the rising edge of CLK
CKE held High will insert wait states. Internal device registers will hold their previous values.
On-chip circuitry is included to ensure that outputs are held in High-Z during power-up.
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