
IBM0418A81QLAB IBM0436A81QLAB
IBM0418A41QLAB IBM0436A41QLAB
Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
trrh3316. 01
11/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 6
Pin Description
SA0-SA18
Address Input
SA0-SA18 for 512Kx18
SA0-SA17 for 256Kx36
SA0-SA17 for 256Kx18
SA0-SA16 for 128Kx36
G
Asynchronous Output Enable
DQ0-DQ35
Data I/O
DQ0-DQ17 for 512Kx18
DQ0-DQ35 for 256Kx36
SS
Synchronous Select
K, K
Differential Input Register Clocks
M1, M2
Clock Mode Inputs- Selects Single or Dual Clock
Operation.
SW
Write Enable, Global
V
REF
(2)
HSTL Input Reference Voltage
SBWa
Write Enable, Byte a (DQ0-DQ8)
V
DD
Power Supply (+3.3V)
SBWb
Write Enable, Byte b (DQ9-DQ17)
V
SS
Ground
SBWc
Write Enable, Byte c (DQ18-DQ26)
V
DDQ
Output Power Supply
SBWd
Write Enable, Byte d (DQ27-DQ35)
ZZ
Asynchronous Sleep Mode
TMS,TDI,TCK
IEEE 1149.1 Test Inputs (LVTTL levels)
ZQ
Output Driver Impedance Control
TDO
IEEE 1149.1 Test Output (LVTTL level)
NC
No Connect
Ordering Information
Part Number
Organization
Speed
Leads
IBM0418A41QLAB - 3
256K x 18
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A41QLAB - 4
256K x 18
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A41QLAB - 5
256K x 18
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0436A41QLAB - 3
128K x 36
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A41QLAB - 4
128K x 36
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A41QLAB - 5
128K x 36
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0418A81QLAB - 3
512K x 18
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A81QLAB - 4
512K x 18
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A81QLAB - 5
512K x 18
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0436A81QLAB -3
256K x 36
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A81QLAB -4
256K x 36
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A81QLAB -5
256K x 36
2.25ns Access /5.0ns Cycle
7 x 17 BGA