參數(shù)資料
型號(hào): HYS72T64400EFD-3S-B2
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, DMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 20/41頁
文件大?。?/td> 2306K
代理商: HYS72T64400EFD-3S-B2
HYS72T[64/128/256]4[0/2]0EFD–[25F/3S]–B2
Fully-Buffered DDR2 SDRAM Modules
Internet Data Sheet
Rev.1.00, 2007-12-12
27
06132007-KAU4-NN52
TABLE 17
PC2–5300–555
Product Type
HYS72T
644
00EF
D
–3S–
B
2
HYS72T
128
420EF
D
–3
S–B2
HYS72T
256
420EF
D
–3
S–B2
Organization
512MB
1 GByte
2 GByte
×72
1 Rank (
×8)
2 Ranks (
×8)
2 Ranks (
×4)
Label Code
PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
0
SPD Size CRC / Total / Used
92
1
SPD Revision
11
2
Key Byte / DRAM Device Type
09
3
Voltage Level of this Assembly
12
4
SDRAM Addressing
44
48
5
Module Physical Attributes
23
6
Module Type
07
7
Module Organization
09
11
10
8
Fine Timebase (FTB) Dividend and Divisor
00
9
Medium Timebase (MTB) Dividend
01
10
Medium Timebase (MTB) Divisor
04
11
t
CK.MIN (min. SDRAM Cycle Time)
0C
12
t
CK.MAX (max. SDRAM Cycle Time)
20
13
CAS Latencies Supported
33
14
t
CAS.MIN (min. CAS Latency Time)
3C
15
Write Recovery Values Supported (WR)
42
16
t
WR.MIN (Write Recovery Time)
3C
17
Write Latency Times Supported
72
18
Additive Latency Times Supported
50
19
t
RCD.MIN (min. RAS# to CAS# Delay)
3C
20
t
RRD.MIN (min. Row Active to Row Active Delay)
1E
21
t
RP.MIN (min. Row Precharge Time)
3C
22
t
RAS and tRC Extension
000000
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