參數(shù)資料
型號： HYS72T64400EFD-3S-B2
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, DMA240
封裝： GREEN, DIMM-240
文件頁數(shù)： 10/41頁
文件大?。?/td> 2306K
代理商： HYS72T64400EFD-3S-B2
HYS72T[64/128/256]4[0/2]0EFD–[25F/3S]–B2
Fully-Buffered DDR2 SDRAM Modules
Internet Data Sheet
Rev.1.00, 2007-12-12
18
06132007-KAU4-NN52
TABLE 11
FB-DIMM Latency Range
TABLE 12
Environmental Parameters
Parameter
DDR2–800D
DDR2–667D
Unit
Note
Min.
Nom.
Max.
Min.
Typ.
Max.
tC2D_DIMM
Tbd
19.35
Tbd
17.5
21
21.5
ns
1)2)
1) For DDR-800D and DDR-800E no Jedec Standart values are avalible for Min. and Max parameter.
2) Measured delay at FBDIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector
pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) – [CL (DRAM CAS
latency) value] * [frame clock period – AL (DRAM additional latency) value * frame clock period].
tRESAMPLE_DIMM_SB
Tbd
1.68
Tbd
1.4
1.69
2.4
ns
2)3)
3) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8 (connector pins 102
& 103) and the center of the 1st UI of the same frame on the secondary southbound lane 8 (connector pins 222 & 223).
tRESAMPLE_DIMM_NB
Tbd
1.48
Tbd
1.3
1.73
2.3
ns
2)4)
4) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
tRESYNC_DIMM_SB
Tbd
2.66
Tbd
2.5
2.8
3.7
ns
2)5)
5) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
tRESYNC_DIMM_NB
Tbd
2.54
Tbd
2.4
2.8
3.6
ns
2)6)
6) Measured delay at FBDIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector
pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) – [CL (DRAM CAS
latency) value] * [frame clock period – AL (DRAM additional latency) value * frame clock period].
Parameter
Symbol
Rating
Units
Notes
Operating Temperature
TOPR
See Note
1)
1) The designer must meet the case temperature specifications for individual module components.
Operating Humidity (relative)
HOPR
10 to 90
%
2)
2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Storage Temperature
TSTG
-50 to +100
°C
Storage Humidity (without condensation)
HSTG
5 to 95
%
Barometric pressure (operating)
PBAR
3050
m
Barometric pressure (storage)
PBAR
14240
m
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