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| 型號： | HYS72T64000EP-3.7-B2 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 3411K |
| 代理商： | HYS72T64000EP-3.7-B2 |
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.02, 2008-06
28
07312007-HYD2-P177
TABLE 19
Definitions for
I
DD
Distributed Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5D
Self-Refresh Current
CKE
≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
I
DD6 current values are guaranteed up to TCASE of 85 °C max.
I
DD6
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out = 0 mA.
I
DD7
1)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2)
I
DD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for
I
DD see Table 19
4) For two rank modules: All active current measurements in the same
I
DD current mode. The other rank is in IDD2P Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6)
I
DD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
Parameter
Description
LOW
V
IN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level.
FLOATING
Inputs are
V
REF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Parameter
Symbol Note
1)2)
3)4)5)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64000EU-2.5-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-25F-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3.7-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3S-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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