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參數(shù)資料
| 型號： | HYS72T64000EP-3.7-B2 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 3411K |
| 代理商： | HYS72T64000EP-3.7-B2 |
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.02, 2008-06
24
07312007-HYD2-P177
12) The
t
HZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
HZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
14) 0 °C
≤ T
CASE ≤ 85 °C.
15) 85
°C < T
CASE ≤ 95 °C.
16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x
t
REFI.
17) The
t
RRD timing parameter depends on the page size of the DRAM organization.
18) The maximum limit for the
t
WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum
t
WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the
t
WR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value.
t
DAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
FIGURE 2
Method for Calculating Transitions and Endpoint
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64000EU-2.5-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-25F-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3.7-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3S-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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