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參數(shù)資料
| 型號： | HYS72D16500GR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Low Profile DDR SDRAM-Modules |
| 中文描述： | 超薄DDR內(nèi)存模塊 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 803K |
| 代理商： | HYS72D16500GR |
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HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
Application Note
Data Sheet
26
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200
μ
sec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(
t
(ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. The system applies Self Refresh entry command.
(CKE
→
Low, CS
→
Low, RAS
→
Low, CAS
→
Low, WE
→
High)
Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.The system sets RESET at a valid
low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-
level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation
to a specific clock edge is not required.
2. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (
t
(INACT) )
.
The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
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PDF描述 |
|---|---|
| HYS72D32501GR-7-A | Low Profile DDR SDRAM-Modules |
| HYS72D16500GR-8-A | Low Profile DDR SDRAM-Modules |
| HYS72D32500GR-7F-B | Low Profile Registered DDR-I SDRAM-Modules |
| HYS72D128520GR-8-B | Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:4 RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D16500GR-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYS72D16500GR-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Low Profile DDR SDRAM-Modules |
| HYS72D16500GR-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYS72D16500GR-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Low Profile DDR SDRAM-Modules |
| HYS72D256020GR-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?2GB (256Mx72) PC2100 2-bank available 3Q02? |
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