參數(shù)資料
型號(hào): HYS72D128520GR-8-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:4 RoHS Compliant: Yes
中文描述: 超薄注冊(cè)的DDR - SDRAM的我模塊
文件頁(yè)數(shù): 18/22頁(yè)
文件大?。?/td> 409K
代理商: HYS72D128520GR-8-B
HYS 72Dxx5xxGR-7F/7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
18
2002-08-16 (0.91)
APPLICATION NOTE:
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up
and to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal
;
the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-
Z
state (eliminating risk of high current dissipa-
tions and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-
Locked Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other
SDRAM inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low
level, all the register outputs are forced to a low level, and all differential register input receivers are powered
down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven
from the system as an asynchronous signal according to the attached details. Using this function also permits the
system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs
stay in Self Refresh mode.
The function for RESET is as follows:
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the
'
Q
'
signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until acti-
vated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of
20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operat-
ing frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High
Z
High
Z
X
Illegal input
conditions
L
X
or Hi-
Z
X
or Hi-
Z
X
or Hi-
Z
L
X
: Don’t care, Hi-
Z
: High Impedance, Qo: Data latched at the previous of CK
risning and CK falling
相關(guān)PDF資料
PDF描述
HYS72D64000GR-7-B 2.5 V 184-pin Registered DDR-I SDRAM Modules
HYS72D128020GR-7-B Modular Connector; No. of Contacts:8; Approval Categories:Fire-Retardant UL 94V-0 Rated; Body Material:Plastic; Color:Blue; Contact Material:Phosphor Bronze; Contact Termination:Punchdown RoHS Compliant: Yes
HYS72D128021GR-7-B Connector Wall Plate; Color:White; Leaded Process Compatible:Yes; No. of Ports:4 RoHS Compliant: Yes
HYS72D128021GR-8-B Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:6 RoHS Compliant: Yes
HYS72D64020GR-7-B 2.5 V 184-pin Registered DDR-I SDRAM Modules
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