參數(shù)資料
型號(hào): HYS 72V64220GU
廠商: SIEMENS AG
英文描述: 3.3 V 64M 72-Bit SDRAM Modules(3.3 V 64M 64/72-Bit 2 個(gè)存儲(chǔ)體的 SDRAM 模塊)
中文描述: 3.3伏6400 72位SDRAM模塊(3.3伏6400 64/72-Bit 2個(gè)存儲(chǔ)體的內(nèi)存模塊)
文件頁數(shù): 10/17頁
文件大小: 131K
代理商: HYS 72V64220GU
HYS 64/72V64220GU
SDRAM-Modules
Data Book
10
3.00
AC Characteristics
3), 4)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8A
PC100-322
-8B
PC100-323
min.
max.
min.
max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
10
12
10
15
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
f
CK
100
83
100
66
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
t
AC
6
6
6
7
ns
ns
4), 5)
Clock High Pulse Width
t
CH
t
CL
3
3
ns
6)
Clock Low Pulse Width
3
3
ns
6)
Setup and Hold Parameters
Input Setup Time
t
IS
t
IH
t
SB
t
PDE
t
RSC
t
T
2
2
ns
7)
Input Hold Time
1
1
ns
7)
Power Down Mode Entry Time
1
1
CLK
8)
Power Down Mode Exit Setup Time
1
1
CLK
9)
Mode Register Setup Time
2
2
CLK
Transition Time (rise and fall)
1
1
ns
Common Parameters
Row to Column Delay Time
t
RCD
t
RP
t
RAS
t
RC
t
RRD
20
20
ns
Row Precharge Time
20
30
ns
Row Active Time
50
100k
60
100k
ns
Row Cycle Time
70
80
ns
Activate (a) to Activate (b) Command
Period
16
20
ns
CAS(a) to CAS(b) Command Period
t
CCD
1
1
CLK
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