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| 型號(hào)： | HYMR1848-745 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 48M X 18 RAMBUS MODULE, DMA84 |
| 封裝： | RIMM-184 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | HYMR1848-745 |
Page 8
Rev. 0.2 / Jan. 99
Preliminary
HYMR1648/1848 Series
Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM datasheet for
detailed timing diagrams.
Parameter
Description
Min
-40
-800
Min
-45
-800
Min
-45
-711
Min
-50
-711
Min
-53
-600
Max
Units
tRC
Row Cycle time of RDRAM banks -the interval between ROWA
packets with ACT commands to the same bank.
28
-
tCYCLE
tRAS
RAS-asserted time of RDRAM bank - the interval between
ROWA packet with ACT command and next ROWR packet with
PRERa command to the same bank.
a. Or equivalent PREC or PREX command.
20
60
sb
b. This is a constraint imposed by the core, and is therefore in units of
s rather than t
CYCLE.
tCYCLE
tRP
Row Precharge time of RDRAM banks - the interval between
ROWR packet with PRERa command and next ROWA packet
with ACT command to the same bank.
8
-
tCYCLE
tPP
Precharge-to-precharge time of RDRAM device - the interval
between successive ROWR packets with PRERa commands to any
banks of the same device.
8
-
tCYCLE
tRR
RAS-to-RAS time of RDRAM device - the interval between suc-
cessive ROWA packets with ACT commands to any banks of the
same device.
8
-
tCYCLE
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT
command to COLC packet with RD or WR command). Note - the
RAS-to-CAS delay seen by the RDRAM core (tRCD,CORE) is
equal to tRCD,CORE = 1 + tRCD because of differences in the row
and column paths through the RDRAM interface.
7
9
7
9
7
-
tCYCLE
tCAC
CAS Access delay - the minimum interval from RD command to
Q read data.
8
12
tCYCLE
tCWD
CAS Write Delay (interval from WR command to D write data.
6
tCYCLE
tCC
CAS-to-CAS time of RDRAM bank - the interval between succes-
sive COLC commands).
4
-
tCYCLE
tPACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
tCYCLE
tRTR
Interval from COLC packet with WR command to COLC packet
which causes retire, and to COLM packet with bytemask.
8
-
tCYCLE
tOFFP
The interval (offset) from COLC packet with RDA command, or
from COLC packet with retire command (after WRA automatic
precharge), or from COLX packet with PREX command to the
equivalent ROWR packet with PRER.
4
tCYCLE
tRDP
Interval from last COLC packet with RD command to ROWR
packet with PRER.
4
-
tCYCLE
tRTP
Interval from last COLC packet with automatic retire command to
ROWR packet with PRER.
4
-
tCYCLE
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