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參數(shù)資料
| 型號： | HYMR1848-745 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 48M X 18 RAMBUS MODULE, DMA84 |
| 封裝： | RIMM-184 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 112K |
| 代理商： | HYMR1848-745 |
Page 6
Rev. 0.2 / Jan. 99
Preliminary
HYMR1648/1848 Series
Absolute Maximum Ratings
DC Recommended Electrical Conditions
AC Electrical Specifications
Symbol
Parameter
Min
Max
Unit
VI,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
VDD + 0.3
V
VDD,ABS
Voltage on VDD with respect to Gnd
- 0.5
VDD + 1.0
V
TSTORE
Storage temperature
- 50
100
°C
Symbol
Parameter and Conditions
Min
Max
Unit
VDD
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
VCMOS
CMOS I/O pin power supply - 2.5V controllers:
- for 1.8V controllers:
2.5 - 0.13
1.8 - 0.1
2.5 + 0.25
1.8 + 0.2
V
VREF
Reference voltage
1.4 - 0.2
1.4 + 0.2
V
VIL
RSL input low voltage
VREF - 0.5
VREF - 0.2
V
VIH
RSL input high voltage
VREF + 0.2
VREF + 0.5
V
VIL,CMOS
CMOS input low voltage
- 0.3
0.5VCMOS - 0.25
V
VIH,CMOS
CMOS input high voltage
0.5VCMOS + 0.25
VCMOS + 0.3
V
VOL,CMOS
CMOS output low voltage @ IOL,CMOS = 1mA
0.3
V
VOH,CMOS
CMOS output high voltage @ IOH,CMOS = -0.25mA
VCMOS - 0.3
V
IREF
VREF current @ VREF,MAX
-160
160
A
ISCK,CMD
CMOS input leakage current @ (0
≤ V
CMOS ≤ VDD)
-160
160
A
ISIN,SOUT
CMOS input leakage current @ (0
≤ V
CMOS ≤ VDD)
-10.0
10.0
A
Symbol
Parameter and Conditions
Min
Max
Unit
Z
Module Impedance
25.2
30.8
Ohms
TPD
Propagation Delay, all RSL signals
-
2.1
ns
T
PD
Propagation delay variation of RSL signals with respect to an average clock delay a
a. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN).
-0.01
0.01
ns
T
PD-CMOS
Propagation delay variation of SCK and CMD signals with respect to an average clock
delay a
-0.1
0.1
ns
Vα/VIN
Attenuation Limit
13.5
%
VXF/VIN
Forward crosstalk coefficient (300ps input risetime 20%-80%)
0.8
%
VXB/VIN
Backward crosstalk coefficient (300ps input risetime 20%-80%)
1
%
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