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| 型號： | HYMD264G726A4-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | 5.250 X 1.700 X 0.150 INCH, DIMM-184 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 257K |
| 代理商： | HYMD264G726A4-H |
HYMD264G726A(L)4-M/K/H/L
Rev. 0.2/May. 02
10
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Parameter
Symbol
DDR266(2-2-2)
DDR266A
DDR266B
DDR200
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Input Setup Time (fast slew rate)
tIS
0.9
-
0.9
-
0.9
-
1.1
-
ns 2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.9
-
0.9
-
0.9
-
1.1
-
ns 2,3,5,6
Input Setup Time (slow slew rate)
tIS
1.0
-
1.0
-
1.0
-
1.1
-
ns 2,4,5,6
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
1.0
-
1.1
-
ns 2,4,5,6
Input Pulse Width
tIPW
2.2
2.5
ns
6
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge of DQS-
In
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In
(DQ & DM)
tDS
0.5
-
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.5
-
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
2-
CK
Exit Self Refresh to Any Execute
Command
tXSC
200
-
200
-
200
-
200
-
CK
8
Average Periodic Refresh Interval
tREFI
-
15.6
-
15.6
-
15.6
-
15.6
us
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
0.5
0
0.4
+50
0
0.3
+100
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYMD264G726A4-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mx72|2.5V|M/K/H/L|x18|DDR SDRAM - Low Profile Registered DIMM 512MB |
| HYMD264G726A4-M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4M-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:Low Profile Registered DDR SDRAM DIMM |
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