
PC133 SDRAM SO DIMM
Rev. 0.3/Dec. 01
6
HYM71V8M635HC(L)T6 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
NOTE
-K
-H
-K
-H
BYTE0
# of Bytes Written into Serial Memory at Module
Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
SDRAM
04h
BYTE3
# of Row Addresses on This Assembly
12
0Ch
1
BYTE4
# of Column Addresses on This Assembly
9
09h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @/CAS Latency=3
7.5ns
75h
BYTE10
Access Time from Clock @/CAS Latency=3
5.4ns
54h
BYTE11
DIMM Configuration Type
None
00h
BYTE12
Refresh Rate/Type
15.625us
/ Self Refresh Supported
80h
BYTE13
Primary SDRAM Width
x16
10h
BYTE14
Error Checking SDRAM Width
None
00h
BYTE15
Minimum Clock Delay Back to Back Random Column
Address
tCCD = 1 CLK
01h
BYTE16
Burst Lenth Supported
1,2,4,8,Full Page
8Fh
2
BYTE17
# of Banks on Each SDRAM Device
4 Banks
04h
BYTE18
SDRAM Device Attributes, /CAS Lataency
/CAS Latency=2,3
06h
BYTE19
SDRAM Device Attributes, /CS Lataency
/CS Latency=0
01h
BYTE20
SDRAM Device Attributes, /WE Lataency
/WE Latency=0
01h
BYTE21
SDRAM Module Attributes
Neither Buffered nor Registered
00h
BYTE22
SDRAM Device Attributes, General
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
0Eh
BYTE23
SDRAM Cycle Time @/CAS Latency=2
7.5ns
10ns
75h
A0h
BYTE24
Access Time from Clock @/CAS Latency=2
5.4ns
6ns
54h
60h
BYTE25
SDRAM Cycle Time @/CAS Latency=1
-
00h
BYTE26
Access Time from Clock @/CAS Latency=1
-
00h
BYTE27
Minimum Row Precharge Time (tRP)
15ns
20ns
0Fh
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
0Fh
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
15ns
20ns
0Fh
14h
BYTE30
Minimum /RAS Pulse Width (tRAS)
45ns
2Dh
BYTE31
Module Bank Density
64MB
10h
BYTE32
Command and Address Signal Input Setup Time
1.5ns
15h
BYTE33
Command and Address Signal Input Hold Time
0.8ns
08h
BYTE34
Data Signal Input Setup Time
1.5ns
15h
BYTE35
Data Signal Input Hold Time
0.8ns
08h
BYTE36
~61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
Intel SPD 1.2B
12h
3, 8
BYTE63
Checksum for Byte 0~62
-
65
A6h
BYTE64
Manufacturer JEDEC ID Code
Hynix JEDED ID
ADh
BYTE65
~71
....Manufacturer JEDEC ID Code
Unused
FFh
BYTE72
Manufacturing Location
HSI(Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
HSS(singapore)
Asia Area
0*h
1*h
2*h
3*h
4*h
5*h
19