參數(shù)資料
型號(hào)： HYE18P32161AC
廠商： INFINEON TECHNOLOGIES AG
英文描述： 32M Asynchronous/Page CellularRAM
中文描述： 32M的異步/頁(yè)的CellularRAM
文件頁(yè)數(shù)： 31/33頁(yè)
文件大小： 641K
代理商： HYE18P32161AC
Data Sheet
31
V2.0, 2003-12-16
HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Appendix B: S/W Register Entry Mode (“4-cycle method”)
6
Appendix B: S/W Register Entry Mode (“4-cycle method”)
Other than ZZ-controlled SCR operation, CellularRAM supports software (S/W) method as an alternative to
access the control registers. Since S/W register entry mode consists of 4 consecutive access cycles to top memory
location (all addresses are “1”), it is often referred as “4-cycle method”. 4-cycles starts from 2 back-to-back read
cycles (initializing command identification) followed by one write cycle (command identification completed and
refresh control register is accessed), then final write cycle for configuring the RCR by the given input or read cycle
to check the content of the register through DQ pins. It does function the configuration of control register bits like
the way with dedicated pin, ZZ method, but there are a few differences from ZZ-controlled method as follow;
Register read mode (checking content) is supported with S/W register entry as well as register write (program).
The mode bits for control register are supplied through DQ <15:0> instead of address pins in ZZ-controlled.
Though each register has 21-bits (A<20:0>) for 32M CellularRAM, only low 16-bit registers becomes valid
during S/W method.
The valid selection of refresh control register, RCR, is done with the state of DQ<15:0> given at 3rd cycle.
(“00h”)
Since S/W register entry asks for 4 complete access cycles in a row and the device is designed operating with
internally regulated supply which is going to be discharged in deep power-down (DPD) mode,
DPD function
is not supported
with this programming method.
The method is realized by the device exactly when 2 consecutive read cycles to top memory location is
followed by write cycle to the same location, so that any exceptional cycle combination - not only access mode,
but also the number of cycles - will fail in invoking the register entry mode properly.
Figure 20
S/W Register Entry timing (Address input = 1FFFFFh)
Don't Care
Amax-A0
All “1”s
CS
UB, LB
OE
WE
DQ15-DQ0
t
RC
ADV#
All “1”s
All “1”s
0000h(RCR)
All `
Register bits
Read to top memory location (1
st
)
Read to top memory location (2nd)
Wait for next write to confirm S/W register entry
Write to top memory location
Select RCR
Write or Read to top memory location
(Write) Configure RCR by DQ inputs
(Read) Output RCR contents through DQ
(Cycle Type)
(Function)
t
WC
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