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參數(shù)資料
| 型號： | HYE18P32161AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32M Asynchronous/Page CellularRAM |
| 中文描述： | 32M的異步/頁的CellularRAM |
| 文件頁數(shù)： | 26/33頁 |
| 文件大?。?/td> | 641K |
| 代理商： | HYE18P32161AC |
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HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
Data Sheet
26
V2.0, 2003-12-16
2.6
Deep Power Down Mode Entry/ Exit
To put the device in deep power down mode, it is required to comply with 2-step operation. At first, the DPD mode
bit (RCR.bit4) has be programmed to be enabled in the Refresh Configuration Register through SCR command.
When DPD entry is really required, ZZ pin must be asserted to low for longer than 10μs while CS1 sets to high as
shown in Figure 15. Between these 2 steps, any normal operations are permitted. Once the device enters into this
extreme low power mode, current consumption is cut down to less than 25μA.
Please note that 2 step operation for DPD entry is not designed to take place at a time when ZZ is held low. In
case of back-to-back operation to perform 2 steps, it is required to meet ZZ precharge time (t
ZPH
).
All internal voltage generators inside the CelllularRAM are switched off and the internal self-refresh is stopped.
This means that all stored information will be lost in any time. The device will remain in DPD mode as long as ZZ
is held low. To exit the Deep Power Down mode, it is needed to simply bring ZZ to high voltage level. A guard time
of at least 150μs (t
R
) has to be met where no commands beside DESELECT must be applied to re-enter standby
or idle mode.
Figure 16
Deep Power Down Entry/ Exit
Table 8
DPD/ ZZ Timing Table
2.7
General AC Input/Output Reference Waveform
The input timings refer to a midlevel of
V
DDQ
/2 while as output timings refer to midlevel
V
DDQ
/2. The rising and
falling edges are 10 - 90% and < 2 ns.
Parameter
Symbol
70 & 85
Unit
Notes
Min.
5
5
10
150
Max.
–
–
–
–
CS1 high setup time to ZZ low
ZZ precharge time
ZZ active for DPD entry
Recovery time from DPD exit
t
CDZZ
t
ZPH
t
ZZMIN
t
R
ns
ns
μs
μs
–
–
–
–
Don't Care
CS1
ZZ
t
ZZMIN
t
CDZZ
t
R
Exiting DPD
Device in DPD
(maintaining)
Entering DPD
t
ZPH
(/ZZ high time is required between step 1 and 2)
(any normal operation is allowed in between)
Step 1 (SCR)
RCR.bit4 should
be programmed
to enable DPD
Step 2
/ZZ low for
longer than
tZZmin
相關(guān)PDF資料 |
PDF描述 |
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| HYE18P32161ACL70 | JT 23C 21#20 2#16 SKT PLUG |
| HYE18P32161ACL85 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:11; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| HYE18P32161AC-70 | 32M Asynchronous/Page CellularRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYE18P32161AC-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
| HYE18P32161AC-85 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
| HYE18P32161ACL70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
| HYE18P32161ACL85 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
| HYE25L128160AC-7.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM |
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