參數(shù)資料
型號: HYB3164405T-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 16M x 4-Bit Dynamic RAM
中文描述: 16M X 4 EDO DRAM, 50 ns, PDSO34
文件頁數(shù): 8/32頁
文件大?。?/td> 473K
代理商: HYB3164405T-50
Semiconductor Group
96
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Average Vcc supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Average Vcc supply current,
during
hyperpage mode (EDO):
-60 ns version
(RAS =
V
IL
, CAS, address cycling: tHPC=tHPC min.)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
I
CC3
110 (140)
100 (120)
mA
mA
2) 4)
-50 ns version
I
CC4
115 (150)
100 (120)
mA
mA
2) 3) 4)
I
CC5
200
A
Average Vcc supply current, during CAS-before-
RAS refresh mode:
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
-50 ns version
I
CC6
110 (140)
100 (120)
mA
mA
2) 4)
I
CC7
400
A
Capacitance
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WRITE, OE)
7
pF
I/O capacitance (I/O1-I/O4)
7
pF
DC Characteristics
(cont’d)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
相關(guān)PDF資料
PDF描述
HYB3164405T-60 High-Speed Fully-Differential Amplifiers 8-MSOP -40 to 85
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HYB3165405BTL-60 Wideband, Low Distortion Fully Differential Amplifier with Shutdown 8-SOIC -40 to 85
HYB3165405T-50 16M x 4-Bit Dynamic RAM
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