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參數(shù)資料
| 型號： | HYB314405BJL-70 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 1M x 4-Bit Dynamic RAM |
| 中文描述： | 1M X 4 EDO DRAM, 70 ns, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-26 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | HYB314405BJL-70 |
Semiconductor Group
6
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
Standby
V
CC
supply current
(RAS = CAS = WE =
V
CC
– 0.2 V)
Average
V
CC
supply current during
CAS before RAS refresh mode
I
CC5
–
1
200
mA
μ
A
mA
1)
L-version
2)4)
-50 version
-60 version
-70 version
I
CC6
–
–
–
70
60
55
For Low Power Version only:
Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE =
V
CC
– 0.2 V or 0.2 V,
A0 to A10 =
V
CC
– 0.2 V or 0.2 V;
D
I
=
V
CC
– 0.2 V or 0.2 V or open,
t
RC
= 125
μ
s,
t
RAS
=
t
RAS
min = 1
μ
s)
I
CC7
–
250
μ
A
–
AC Characteristics
5)6)
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
89
–
104
–
124
–
ns
RAS precharge time
35
–
40
–
50
–
ns
RAS pulse width
50
10 k
60
10 k
70
10 k
ns
CAS pulse width
8
10 k
10
10 k
12
10 k
ns
Row address setup time
0
–
0
–
0
–
ns
Row address hold time
8
–
10
–
10
–
ns
Column address setup time
0
–
0
–
0
–
ns
Column address hold time
8
–
10
–
12
–
ns
RAS to CAS delay time
12
37
14
45
14
53
ns
RAS to column address delay
time
10
25
12
30
12
35
ns
DC Characteristics
(cont’d)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
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