參數(shù)資料
型號: HYB314171BJ-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
中文描述: 256K X 16 FAST PAGE DRAM, 50 ns, PDSO40
封裝: 0.400 INCH, PLASTIC, SOJ-40
文件頁數(shù): 10/24頁
文件大?。?/td> 1339K
代理商: HYB314171BJ-50
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
10
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS =
V
il
. In case of
I
CC4
it can be changed once or less during
a page mode cycle
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 5 ns.
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with a load equivalent to 100 pF and at Voh=2.0V (Ioh=-2mA), Vol=0.8V (Iol=2mA).
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
,
t
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
13) Either
t
DZC
or
t
DZO
must be satisfied.
43) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
>
t
,
t
>
t
and
t
>
t
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
相關(guān)PDF資料
PDF描述
HYB314171BJ-50- 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB314171BJ-60 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB314171BJ-70 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB314171BJL-50 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
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HYB314171BJ-60 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
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HYB314171BJL-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
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