參數(shù)資料
型號(hào)： HYB25D256160TCL-75
廠商： INFINEON TECHNOLOGIES AG
英文描述： MEMORY SPECTRUM
中文描述： 記憶譜
文件頁數(shù)： 69/94頁
文件大?。?/td> 3326K
代理商： HYB25D256160TCL-75
Data Sheet
71
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Write postamble
tWPST
0.40
0.60
0.40
0.60
tCK 2)3)4)5)11)
Write recovery time
tWR
15
—
15
—
ns
2)3)4)5)
Internal write to read command
delay
tWTR
2—
1
—
tCK 2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
—
200
—
tCK 2)3)4)5)
1) 0
°C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate
≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until
VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
VTT.
6) For each of the terms, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock
cycle time.
7)
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate
≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW at this time, depending on
tDQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Table 22
AC Timing - Absolute Specifications for PC2700
Parameter
Symbol –7
Unit
Note/Test
Condition 1)
DDR266A
Min.
Max.
DQ output access time from CK/CK
tAC
–0.75
+0.75
ns
2)3)4)5)
CK high-level width
tCH
0.45
0.55
tCK
2)3)4)5)
Clock cycle time
tCK
7.5
12
ns
CL = 3.03)4)5)
7.5
12
ns
CL = 2.52)3)4)5)
7.5
12
ns
CL = 2.02)3)4)5)
CK low-level width
tCL
0.45
0.55
tCK
2)3)4)5)
Auto precharge write recovery + precharge
time
tDAL
(
tWR/tCK)+(tRP/tCK)—
tCK
2)3)4)5)6)
DQ and DM input hold time
tDH
0.5
—
ns
2)3)4)5)
DQ and DM input pulse width (each input)
tDIPW
1.75
—
ns
2)3)4)5)6)
Table 21
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition 1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
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