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參數(shù)資料
| 型號： | HYB25D256160CE-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbit Double Data Rate SDRAM |
| 中文描述： | 256兆雙倍數(shù)據速率SDRAM |
| 文件頁數(shù)： | 59/94頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | HYB25D256160CE-5 |
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Data Sheet
62
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Operating Conditions
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 14
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test Condition
min. typ. max.
Voltage on I/O pins relative to
VSS
VIN, VOUT –0.5 –
VDDQ+0.5 V
–
Voltage on inputs relative to
VSS
VIN
–1
–
+3.6
V
–
Voltage on
VDD supply relative to VSS
VDD
–1
–
+3.6
V
–
Voltage on
VDDQ supply relative to VSS
VDDQ
–1
–
+3.6
V
–
Operating temperature (ambient)
TA
0–
+70
°C–
Storage temperature (plastic)
TSTG
-55
–
+150
°C–
Power dissipation (per SDRAM component)
PD
–1.5
–
W
–
Short circuit output current
IOUT
–50
–
mA
–
Table 15
Input and Output Capacitances
Parameter
Symbol
Values
Unit
Note/
Test Condition
Min.
Typ.
Max.
Input Capacitance: CK, CK
CI1
1.5
—
2.5
pF
P-TFBGA-60-12 1)
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only.
VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 ×C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins
are tied to ground.
2.0
—
3.0
pF
P-TSOPII-66 1)
Delta Input Capacitance
CdI1
——0.25
pF
Input Capacitance:
All other input-only pins
CI2
1.5
—
2.5
pF
P-TFBGA-60-12 1)
2.0
—
3.0
pF
P-TSOPII-66 1)
Delta Input Capacitance:
All other input-only pins
CdIO
——0.5
pF
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
—
4.5
pF
P-TFBGA-60-12
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace
matching at the board level.
4.0
—
5.0
pF
P-TSOPII-66 1)2)
Delta Input/Output Capacitance:
DQ, DQS, DM
CdIO
——0.5
pF
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