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參數(shù)資料
| 型號(hào)： | HYB25D256160BT-7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbit Double Data Rate SDRAM |
| 中文描述： | 256兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁(yè)數(shù)： | 16/94頁(yè) |
| 文件大?。?/td> | 3326K |
| 代理商： | HYB25D256160BT-7 |
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Data Sheet
23
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
MR
Mode Register Definition
(BA[1:0] = 00B)
BA1
BA0
A12
A11
A10
A9A8A7A6A5
A4A3A2A1A0
0
OPERATING MODE
CL
BT
BL
reg. addr
w
Field
Bits
Type1)
1) w = write only register bit
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command; see
Note: All other bit combinations are RESERVED.
001 2
010 4
011 8
BT
3
Burst Type
See Table 7 for internal address sequence of low order address bits; see
0
Sequential
1
Interleaved
CL
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
010 2
011 3
101 1.5
Note: DDR200 components only
110 2.5
MODE [12:7]
Operating Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
000000
Normal Operation without DLL Reset
000010
Normal Operation with DLL Reset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256160BT-7F | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256160BT-8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:?256Mbit (16Mx16) DDR200 (2-2-2)? |
| HYB25D256160BTL-5 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256MBit Double Data Rata SDRAM |
| HYB25D256160BTL-5A | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256MBit Double Data Rata SDRAM |
| HYB25D256160BTL-6 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
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