參數(shù)資料
型號(hào): HYB25D128800ATL-7
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù): 66/85頁(yè)
文件大?。?/td> 3085K
代理商: HYB25D128800ATL-7
–0.5
+0.5
Data Sheet
66
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 18
Parameter
AC Operating Conditions
1)
Symbol
Values
Unit Note/
Test
Condition
2)3)
Min.
Max.
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
V
REF
+ 0.31 —
0.7
0.5
×
V
DDQ
– 0.2
V
V
REF
– 0.31 V
V
DDQ
+ 0.6 V
0.5
×
V
DDQ
+ 0.2
2)3)
2)3)4)
V
2)3)5)
1)
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR200 - DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V (DDR400);
0
°
C
T
A
70
°
C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until
V
REF
stabilizes.
4)
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of
V
IX
is expected to equal 0.5
×
V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Table 19
Parameter
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100
Symbol –5
DDR400B
Min.
DQ output access time from CK/
CK
DQS output access time from CK/
CK
CK high-level width
t
CH
CK low-level width
t
CL
Clock Half Period
t
HP
Clock cycle time
t
CK
–6
–7
Unit
Note/ Test
Condition
1)
DDR333
Min.
–0.7
DDR266A
Min.
–0.75
Max.
Max.
+0.7
Max.
+0.75
t
AC
ns
2)3)4)5)
t
DQSCK
–0.5
+0.5
–0.6
+0.6
–0.75
+0.75
ns
2)3)4)5)
0.45
0.45
min. (
t
CL
,
t
CH
) min. (
t
CL
,
t
CH
)
5
8
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
min. (
t
CL
,
t
CH
) ns
7
12
0.55
0.55
t
CK
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
6
12
ns
CL = 3.0
2)3)4)5)
6
12
6
12
7.5
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse
width (each input)
DQ and DM input pulse width
(each input)
Data-out high-impedance time
from CK/CK
Data-out low-impedance time
from CK/CK
Write command to 1
st
DQS
latching transition
t
DH
t
DS
t
IPW
0.4
0.4
2.2
0.45
0.45
2.2
0.5
0.5
2.2
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
t
DIPW
1.75
1.75
1.75
ns
2)3)4)5)6)
t
HZ
+0.7
–0.7
+0.7
+0.75
ns
2)3)4)5)7)
t
LZ
–0.7
+0.7
–0.7
+0.7
–0.75
+0.75
ns
2)3)4)5)7)
t
DQSS
0.72
1.25
0.75
1.25
0.75
1.25
t
CK
2)3)4)5)
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