參數(shù)資料
型號(hào)： HYB25D128800ATL-7
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 55/85頁(yè)
文件大小： 3085K
代理商： HYB25D128800ATL-7
Data Sheet
55
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3) Current state definitions:
Idle: The bank has been precharged, and
t
RP
has been met.
Row Active: A row in the bank has been activated, and
t
RCD
has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when
t
RP
is met. Once
t
RP
is met, the bank is in
the idle state.
Row Activating: Starts with registration of an Active command and ends when
t
RCD
is met. Once
t
RCD
is met, the bank is in
the “row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when
t
RP
has been met. Once
t
RP
is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
t
RP
has been met. Once
t
RP
is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and according to
Table 10
.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied
on each positive clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when
t
RFC
is met. Once
t
RFC
is met, the
DDR SDRAM
is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when
t
MRD
has been met.
Once
t
MRD
is met, the
DDR SDRAM
is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when
t
RP
is met. Once
t
RP
is met, all banks
is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
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