參數(shù)資料
型號(hào): HYB25D128323C-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁數(shù): 43/53頁
文件大?。?/td> 734K
代理商: HYB25D128323C-3
1.0
1.2
1.0
V
REF
- 0.2
0.49
×
V
DDQ
1.0
Data Sheet
43
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Figure 31
Output Test Circuit
1)
T
A
= 0 to 70
°
C;
V
SS
= 0 V
2) Under all conditions,
V
DDQ
must be less than or equal to
V
DD
3) The speed sorts L3.6 and –3.6 support both
V
DD
modes: 2.5V
±
5% and 2.5V – 2.9V
4)
V
DDQ
= 2.5 V -/+5%
5) Typically the value of
V
REF
is expected to be 0.5 *
V
DDQ
of the transmitting device.
V
REF
is expected to track variations in
V
DDQ
6) Peak to peak AC noise on
V
REF
may not exceed 2%
V
REF
(DC)
7)
V
TT
of the transmitting device must track
V
REF
of the receiving device
8) Overshoots of
V
IH
must be limited to a voltage < (
V
DDQ
+ 1.5 V) and a pulse width < 0.33 of the clock pulse
9) Undershoots of
V
IL
must be limited to a voltage > -1.5 V and a pulse width < 0.33 of the clock pulse
Table 15
Parameter
AC Operation Conditions
Symbol
Values
typ. max.
V
REF
V
REF
+ 0.2
0.51
×
V
DDQ
V
Unit Notes
min.
V
REF
+ 0.50
V
REF
+ 0.60
V
REF
+ 0.50
V
SSQ
- 0.3
V
SSQ
- 0.3
V
SSQ
- 0.3
1.2
Input logic high voltage
V
IH
V
DDQ
+ 0.3
V
DDQ
+ 0.3
V
DDQ
+ 0.3
V
REF
- 0.50
V
REF
- 0.60
V
REF
- 0.50
V
DDQ
+ 0.6
V
DDQ
+ 0.6
V
DDQ
+ 0.6
V
DDQ
+ 0.6
V
V
V
V
V
V
V
V
V
V
V
L3.6, L4.5
–5.0
–3, –3.3, –3.6, –4.5
L3.6, L4.5
–5.0
–3, –3.3, –3.6, –4.5
L4.5
L3.6
–4.5, –5.0
–3, –3.3, –3.6, –4.5
V/ns —
Input logic low voltage
V
IL
Clock Differential Input Voltage
(CLK/CLK)
V
ID
Clock Input Crossing Point (CLK/CLK)
I/O Reference Voltage
Input Slew Rate
V
IX
V
REF
r
I
Table 16
Pin
A11.. A0, BA1, BA0, CKE, CS, CAS, RAS, WE
CLK, CLK
Pin Capacitances
min.
1.0
1.0
max.
2.5
2.5
Unit
pF
pF
15 pF
DQ, DQS
+ Vtt = 0.5xV
DDQ
50 Ohm
Test point
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