- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370783 > HYB25D128323C-3 (INFINEON TECHNOLOGIES AG) 128 Mbit DDR SGRAM PDF資料下載
參數(shù)資料
| 型號： | HYB25D128323C-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 18/53頁 |
| 文件大?。?/td> | 734K |
| 代理商： | HYB25D128323C-3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
18
V1.7, 2003-07
The minimum time during which the output data is valid is critical for the receiving device. This also applies to the
Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters
t
QH
and
t
DQSQ
define
the minimum output data valid window.
Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit
from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble”
t
RPRE
.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe
signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble”
t
RPST
.
Figure 6
DQS Timing for Read
3.4.3.2
During a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally
centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data
strobe edges during writes are specified by the setup and hold time parameters of data (
t
QDQSS
&
t
QDQSH
) and data
mask (
t
DMDQSS
&
t
DMDQSH
). The input data is masked in the same cycle when the corresponding DMx signal is high
(i.e. the DMx mask to write latency is zero.)
Operation at Burst Write
Table 4
data strobe signal
Mapping of DQSx and DMx
data mask signal
Controlled data bus
DQS0
DQS1
DQS2
DQS3
DM0
DM1
DM2
DM3
DQ7 .. DQ0
DQ8 .. DQ15
DQ16 .. DQ23
DQ24 .. DQ31
DQx
CLK,
CLK#
DQS
"Preamble"
t
RPRE
"Postamble"
t
RPST
VIH
VTT
VIL
D
D+1
D+2
D+3
VIH
VTT
VIL
t
DQSQ
t
AC
T0
T1
T2
T3
T4
VIH
VIL
t
CH
t
CL
t
CK
t
DQSCK
t
HP
t
QH
t
QHS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128400AT | 128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128400ATL-8 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-6 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-8 | 128 Mbit Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128323C-3.3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。