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參數(shù)資料
| 型號： | HYB25D128160TC-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MEMORY SPECTRUM |
| 中文描述： | 記憶譜 |
| 文件頁數(shù)： | 60/85頁 |
| 文件大小： | 3085K |
| 代理商： | HYB25D128160TC-8 |
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Data Sheet
60
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 14
Parameter
Electrical Characteristics and DC Operating Conditions
Symbol
Min.
Device Supply Voltage
V
DD
Device Supply Voltage
V
DD
Output Supply Voltage
V
DDQ
Output Supply Voltage
V
DDQ
Supply Voltage, I/O Supply
Voltage
V
SSQ
Input Reference Voltage
V
REF
Values
Typ.
2.5
2.6
2.5
2.6
Unit Note/Test Condition
1)
1) 0
°
C
≤
T
A
≤
70
°
C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions,
V
DDQ
must be less than or equal to
V
DD
.
4) Peak to peak AC noise on
V
REF
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
DDQ
.
5)
V
TT
is not applied directly to the device.
V
TT
is a system supply for signal termination resistors, is expected to be set equal
to
V
REF
, and must track variations in the DC level of
V
REF
.
6)
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until
V
REF
stabilizes.
9) Values are shown per component
Max.
2.7
2.7
2.7
2.7
0
2.3
2.5
2.3
2.5
0
V
V
V
V
V
f
CK
≤
166 MHz
f
CK
> 166 MHz
2)
f
CK
≤
166 MHz
3)
f
CK
> 166 MHz
2)3)
—
V
SS
,
0.49
×
V
DDQ
V
DDQ
/ 2
– 50 mV
V
REF
– 0.04
0.5
×
V
DDQ
V
DDQ
/ 2
0.51
×
V
DDQ
V
DDQ
/ 2
+ 50 mV
V
REF
+ 0.04 V
V
f
CK
≤
166 MHz
4)
Input Reference Voltage
V
REF
V
f
CK
> 166 MHz
2)4)
I/O Termination Voltage
(System)
Input High (Logic1) Voltage
V
IH(DC)
Input Low (Logic0) Voltage
V
IL(DC)
Input Voltage Level,
CK and CK Inputs
Input Differential Voltage,
CK and CK Inputs
VI-Matching Pull-up
Current to Pull-down
Current
Input Leakage Current
V
TT
5)
V
REF
+ 0.15
–0.3
–0.3
V
DDQ
+ 0.3
V
REF
– 0.15 V
V
DDQ
+ 0.3
V
8)
8)
V
IN(DC)
V
8)
V
ID(DC)
0.36
V
DDQ
+ 0.6
V
8)6)
VI
Ratio
0.71
1.4
—
7)
I
I
–2
2
μ
A
Any input 0 V
≤
V
IN
≤
V
DD
;
All other pins not under test
= 0 V
8)9)
DQs are disabled;
0 V
≤
V
OUT
≤
V
DDQ
8)
V
OUT
= 1.95 V
8)
Output Leakage Current
I
OZ
–5
5
μ
A
Output High Current,
Normal Strength Driver
Output Low
Current, Normal Strength
Driver
I
OH
—
–16.2
mA
I
OL
16.2
—
mA
V
OUT
= 0.35 V
8)
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