Note:1 Gbit based module
Note:Module based on 512 Mbit or smaller dies
Data Sheet
11
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
K7, 29
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
J3, 40
K8, 28
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:0
Note:Provide the row address for Active commands, and the
column address and Auto Precharge bit for Read/Write
commands, to select one location out of the memory array
in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a Mode
Register Set command.
J2, 41
H2, 42
Address Signal 12
Note:Module based on 256 Mbit or larger dies
Note:Module based on 128 Mbit or smaller dies
Address Signal 13
NC
A13
NC
I
—
SSTL
F9, 17
NC
NC
—
Data Signals
×
4 organization
B7, 5
D7, 11
D3, 56
B3, 62
Data Strobe
×4
organisation
E3, 51
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 3:0
DQS
I/O
SSTL
Data Strobe
Note:Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask
×4
organization
F3, 47
DM
I
SSTL
Data Mask
Note:DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading
Table 2
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function