參數(shù)資料
型號(hào)： HYB25D128160TC-8
廠商： INFINEON TECHNOLOGIES AG
英文描述： MEMORY SPECTRUM
中文描述： 記憶譜
文件頁(yè)數(shù)： 38/85頁(yè)
文件大小： 3085K
代理商： HYB25D128160TC-8
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
38
Rev. 1.0, 2004-04
3.5.3
Write bursts are initiated with a Write command, as shown in
Figure 17
.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is
disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write
command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS
between the Write command and the first rising edge is known as the write preamble; the Low state on DQS
following the last data-in element is known as the write postamble. The time between the Write command and the
first corresponding rising edge of DQS (
t
DQSS
) is specified with a relatively wide range (from 75% to 125% of one
clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e.
t
DQSS(min)
and
t
DQSS(max)
).
Figure 18
shows the two extremes of
t
DQSS
for a burst of four. Upon completion of a burst, assuming
no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case,
a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge
of clock following the previous Write command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Write command should be issued x cycles after the first Write command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture).
Figure 19
shows concatenated
bursts of 4. An example of non-consecutive Writes is shown in
Figure 20
. Full-speed random write accesses
within a page or pages can be performed as shown in
Figure 21
. Data for any Write burst may be followed by a
subsequent Read command. To follow a Write without truncating the write burst,
t
WTR
(Write to Read) should be
met as shown in
Figure 22
.
Data for any Write burst may be truncated by a subsequent Read command, as shown in
Figure 23
to
Figure 25
.
Note that only the data-in pairs that are registered prior to the
t
WTR
period are written to the internal array, and any
subsequent data-in must be masked with DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without
truncating the write burst,
t
WR
should be met as shown in
Figure 26
.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in
Figure 27
to
Figure 29
. Note that only the data-in pairs that are registered prior to the
t
WR
period are written to the internal array,
and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent
command to the same bank cannot be issued until
t
RP
is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same burst with Auto Precharge. The
disadvantage of the Precharge command is that it requires that the command and address busses be available at
the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to
truncate bursts.
Writes
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