參數資料
型號: HYB18H1G321AF
廠商: QIMONDA
英文描述: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
中文描述: GDDR3顯卡內存1千兆位GDDR3顯卡內存
文件頁數: 39/48頁
文件大?。?/td> 1406K
代理商: HYB18H1G321AF
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Internet Data Sheet
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
39
5.12
AC Timings for HYB18H1G321AF–10/11/14
TABLE 22
Timing Parameters (HYB18H1G321AF–10/11/14 )
Parameter
CAS
latency
Symbo
l
Limit Values
Unit
Note
–10
–11
-14
min
max
min
max
min
max
Clock and Clock Enable
System frequency
CL = 12
CL =11
CL = 9
f
CK12
f
CK11
f
CK9
t
CH
t
CL
t
HP
450
400
0.45
0.45
0.45
1000
900
0.55
0.55
400
0.45
0.45
0.45
900
0.55
0.55
450
0.45
0.45
0.45
700
0.55
0.55
MHz
MHz
MHz
t
CK
t
CK
t
CK
1)
2)
2)
Clock high level width
Clock low level width
Minimum clock half period
Command and Address Setup and Hold Timing
Address/Command input setup
time
Address/Command input hold time
t
IH
Address/Command input pulse
width
Mode Register Set Timing
Mode Register Set cycle time
Mode Register Set to READ timing
t
MRDR
Row Timing
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command
period
ACT(a) to ACT(b) Command
period (different rank)
Row Precharge Time
Row to Column Delay Time for
Reads
Row to Column Delay Time for
Writes
Four Active Windows within Rank
Column Timing
CAS(a) to CAS(b) Command
period
Internal write to Read Command
Delay
3)
3)
3)4)
t
IS
0.24
0.27
0.35
ns
0.24
0.7
0.27
0.7
0.35
0.7
ns
t
CK
t
IPW
3)
t
MRD
6
12
6
12
6
12
t
CK
t
CK
5)6)
5)
t
RC
t
RAS
t
RRD
37
23
9
35
22
8
34
22
7
t
CK
t
CK
t
CK
7)
t
RRD_RR
1
1
t
CK
t
RP
t
RCDRD
14
13
13
12
12
11
t
CK
t
CK
t
RCDWR
t
RCDWR(Min)
= max(
t
RCDRD(Min)
- (WL + 1)
×
t
CK
;2
×
t
CK
)
t
CK
t
FAW
36
35
35
t
CK
t
CCD
BL/2
BL/2
BL/2
t
CK
8)
t
WTR
7
6
6
t
CK
9)
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