參數(shù)資料
型號: HYB 3117805BSJ-60
廠商: SIEMENS AG
英文描述: 2M×8 - Bit Dynamic RAM 2k Refresh(Hyper Page Mode EDO)
中文描述: 200萬× 8 -位動態(tài)隨機存儲器(200萬× 8位動態(tài)內(nèi)存)
文件頁數(shù): 6/23頁
文件大?。?/td> 176K
代理商: HYB 3117805BSJ-60
HYB 5(3)117805/BSJ-50/-60
2M
×
8 EDO-DRAM
Semiconductor Group
6
1998-10-01
AC Characteristics
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 % /
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
5, 6
Symbol
Limit Values
Unit
Note
-50
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
84
104
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
8
10k
10
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
8
10
ns
RAS to CAS delay time
12
37
14
45
ns
RAS to column address delay
10
25
12
30
ns
RAS hold time
13
15
ns
CAS hold time
40
50
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
1
50
1
50
ns
7
Refresh period
32
32
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
t
RAL
t
RCS
t
RCH
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
OE access time
13
15
ns
Column address to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
Read command hold time referenced to RAS
t
RRH
CAS to output in low-Z
0
0
ns
11
0
0
ns
11
t
CLZ
t
OFF
t
OEZ
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
Output turn-off delay from OE
0
13
0
15
ns
12
相關(guān)PDF資料
PDF描述
HYB 5117805BSJ-50 2M×8 - Bit Dynamic RAM 2k Refresh(Hyper Page Mode EDO)
HYB 5117805BSJ-60 2M×8 - Bit Dynamic RAM 2k Refresh(Hyper Page Mode EDO)
HYB3117805BSJ-60 2M x 8-Bit Dynamic RAM 2k Refresh
HYB314405BJBJL-50- 1M x 4-Bit Dynamic RAM
HYB314405BJ-60 Transistor Array IC; Number of Transistors:4; Package/Case:16-SOIC; C-E Breakdown Voltage:50V; Mounting Type:Surface Mount
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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