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參數(shù)資料
| 型號(hào)： | HY62QF16200ALLF-I-10 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 100 ns, PBGA48 |
| 封裝： | FINE PITCH, BGA-48 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | HY62QF16200ALLF-I-10 |
HY62QF16200A Series
Rev.04 /Jun. 2000
5
TIMING DIAGRAM
READ CYCLE 1(Note 1)
ADDR
OE
CS
UB,LB
Data
Out
Data Valid
tRC
tACS
tCLZ
tOE
tOLZ(5)
tAA
tOH
tBHZ(5)
High-Z
tBA
tBLZ(5)
tOHZ(5)
tCHZ(5)
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,3,4)
CS
tACS
Data Valid
tCLZ(5)
tCHZ(5)
Data
Out
Notes:
1. /WE is high for the Read Cycle.
2. Device is continuously selected. /CS = VIL
3. Address valid is prior to or coincident with /CS transition low
4. /OE = VIL
5. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
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