參數(shù)資料
型號(hào): HY29F002BC-45I
廠商: HYNIX SEMICONDUCTOR INC
元件分類: PROM
英文描述: 256K X 16 FLASH 5V PROM, 45 ns, PQCC32
封裝: PLASTIC, LCC-32
文件頁(yè)數(shù): 37/40頁(yè)
文件大小: 457K
代理商: HY29F002BC-45I
6
HY29F002
Rev. 4.0/Jan. 00
Table 3. HY29F002 Bus Operations Requiring High Voltage 1, 2
Notes:
1. L = V
IL, H = VIH, X = Don’t Care.
See DC Characteristics for voltage levels.
2. Address bits not specified are Don’t Care.
3. See text for additional information.
4. SA = sector address. See Table 1.
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O
3
#
E
C
#
E
O
#
E
W
#
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3
1
:
7
1
[
A
]
9
[
A
]
6
[
A
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1
[
A
]
0
[
A
]
0
:
7
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2
0
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9
2
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H
LL
H
X
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LL
H
0
B
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2
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4
3
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LL
H
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S 4
V
D
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LH
L
=
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x
0
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Low and drive WE# High for a valid read opera-
tion to take place. The device outputs the speci-
fied array data on DQ[7:0].
The HY29F002 is automatically set for reading
array data after device power-up and after a hard-
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from or program data into any sector of
memory that is not marked for erasure. If the host
attempts to read from an address within an erase-
suspended sector, or while the device is perform-
ing an erase or byte program operation, the de-
vice outputs status data instead of array data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read
array data with the same exceptions noted above.
After completing an internal program or internal
erase algorithm, the HY29F002 automatically re-
turns to the read array data mode.
The host must issue a hardware reset or the soft-
ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F002. Writes to the device are performed
by placing the byte address on the device’s ad-
dress inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
latched on the falling edge of WE# or CE#, which-
ever happens later. All data is latched on the ris-
ing edge of WE# or CE#, whichever happens first.
The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F002.
Output Disable Operation
When the OE# input is at V
IH, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F002, it can place the device in the
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