參數(shù)資料
型號: HY27US561M
廠商: Hynix Semiconductor Inc.
英文描述: 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
中文描述: 片256Mbit(32Mx8bit / 16Mx16bit)NAND閃存
文件頁數(shù): 30/44頁
文件大?。?/td> 733K
代理商: HY27US561M
Rev 0.7 / Oct. 2004
30
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Note: (1). The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 32, 33 and 34.
(2). To break the sequential read cycle, CE must be held High for longer than t
EHEL
.
(3). ES = Electronic Signature.
t
RLQV
t
REA
Read Enable Low to Output Valid
Read Enable Access time
Max
35
ns
t
READID
Read ES Access time
t
WHBH
t
R
Write Enable High to Ready/Busy High
Max
10
us
t
WHBL
t
WB
Write Enable High to Ready/Busy Low
Max
100
ns
t
WHRL
t
WHR
Write Enable High to Read Enable Low
Min
60
ns
t
WLWL
t
WC
Write Enable Low to Write
Enable Low
Write Cycle time
Min
50
60
ns
Alt.
Sym-
bol
Sym-
bol
Parameter
3.3V
Device
1.8V
Device
Unit
Figure 21. Command Latch AC Waveforms
Command
tCLHWL
(CLE Setup time)
tELWL
(CE Setup time)
tHWCLL
(CLE Hold time)
tWHEH
(CE Hold time)
tWLWH
tALLWL
(ALE Setup time)
tWHALH
(ALE Hold time)
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
CLE
ALE
I/O
CE
WE
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