HT49R50A
23
November 29, 2000
edges. In the case of counter overflows, the coun-
ter is reloaded from the timer/event counter
preloadregisterandissuesaninterruptrequest,
as in the other two modes, i.e., event and timer
modes.
To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMR0C or TMR1C) should be
set to 1. In the pulse width measurement mode,
the TON is automatically cleared after the
measurement cycle is completed. But in the
other two modes, the TON can only be reset by
instructions. The overflow of the timer/event
counter 0/1 is one of the wake-up sources and
can also be applied to a PFD (Programmable
Frequency Divider) output at PA3 by options.
Only one PFD (PFD0 or PFD1) can be applied to
PA3 by options . No matter what the operation
mode is, writing a 0 to ET0I or ET1I disables the
relatedinterruptservice.WhenthePFDfunction
is selected, executing "CLR [PA].3" instruction to
enable PFD output and executing "SET [PA].3"
instruction to disable PFD output.
In the case of timer/event counter OFF
condition,writingdatatothetimer/eventcounter
preload register also reloads that data to the
timer/eventcounter.Butifthetimer/eventcoun-
ter is turn on, data written to the timer/event
counter is kept only in the timer/event counter
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Timer/event counter 1
Label
(TMR0C)
Bits
Function
0~2 Unused bits, read as "0"
TE
3
To define the TMR0 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
TN2
5
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
TN0
TN1
6
7
To define the operating mode (TN1, TN0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR0C register