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參數(shù)資料
| 型號： | HT49R50A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance High speed Microcontroller(8位、高性能、高速微控制器) |
| 中文描述： | 8位高性能高速微控制器（8位，高性能，高速微控制器） |
| 文件頁數(shù)： | 22/51頁 |
| 文件大?。?/td> | 320K |
| 代理商： | HT49R50A |
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HT49R50A
22
November 29, 2000
Timer/event counter
Two timer/event counters are implemented in
the HT49R50A. Both of them contain an 8-bit
programmable count-up counter.
The timer/event counter 0 clock source may
come from the system clock or system clock/4 or
RTC time-out signal or external source. System
clock source or system clock/4 is selected by op-
tions.
The timer/event counter 1 clock source may
come from TMR0 overflow or system clock or
time base time-out signal or system clock/4 or
external source, and the three former clock
source is selected by options.
The external clock input allows the user to
count external events, measure time intervals
or pulse widths, or to generate an accurate time
base.
The two timer/event counters are operated al-
most in the same manner, except the clock
source and related registers.
There are two registers related to the
timer/event counter 0, i.e., TMR0 ([0DH]) and
TMR0C ([0EH]), and two registers related to
the timer/event counter 1, i.e., TMR1 ([10H],
and TMR1C ([11H]). There are also two physi-
cal registers are mapped to TMR0 (TMR1) loca-
tion; writing TMR0 (TMR1) places the starting
value in the timer/event counter preload regis-
ter, while reading it yields the contents of the
timer/event counter. TMR0C and TMR1C are
timer/event counter control registers used to
define some options.
The TN0 and TN1 bits define the operation
mode.Theeventcountmodeisusedtocountex-
ternal events, which means that the clock
source is from an external (TMR0, TMR1) pin.
The timer mode functions as a normal timer
with the clock source coming from the internal
selected clock source. Finally, the pulse width
measurement mode can be used to count the
high or low level duration of the external signal
(TMR0, TMR1), and the counting is based on
the internal selected clock source.
Intheeventcountortimermode,thetimer/event
counterstartscountingatthecurrentcontentsin
the timer/event counter and ends at FFH. Once
an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and
generates an interrupt request flag (T0F; bit 6 of
INTC0, T1F; bit 4 of INTC1).
In the pulse width measurement mode with
the values of the TON and TE bits equal to
one, after the TMR0 (TMR1) has received a
transient from low to high (or high to low if
the TE bit is "0"), it will start counting until
the TMR0 (TMR1) returns to the original
level and resets the TON. The measured re-
sult remains in the timer/event counter even
if the activated transient occurs again. In
other words, only one cycle measurement can
be made until the TON is set. The cycle mea-
surement will re-function as long as it receives
further transient pulse. In this operation mode,
the timer/event counter begins counting accord-
ing not to the logic level but to the transient
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Timer/event counter 0
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