HT49C50
29
August 18, 1999
Mask option
The following shows 18 kinds of mask options
in the HT49C50. All these options should be de-
fined in order to ensure proper system function-
ing.
Register Bit No. Label Read/Write Reset
Function
RTCC
(09H)
0~2
RT0
RT1
RT2
R/W
0
8 to 1 multiplexer control inputs to select the
real time clock prescaler output
3
Unused bits, this bit must dear to 0
4
QOSC
R/W
0
Control the RTC OSC to oscillate quickly
0 enable
1 disable
5~7
Unused bits, read as 0
RTCC register
No.
Mask Option
1
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as sys-
tem clock.
2
WDT Clock source selection. RTC and Time Base. There are three types of selection: sys-
tem clock/4 or RTC OSC or WDT OSC.
3
WDT enable/disable selection. WDT can be enabled or disabled by mask option.
4
CLR WDT times selection. This option defines how to clear the WDT by instruction. One
time means that the CLR WDT can clear the WDT. Two times means only if both of
the CLR WDT1 and CLR WDT2 have been executed, the WDT can be cleared.
5
Time Base time-out period selection. The Time Base time-out period ranges from
clock/2
to clock/2
. Clock means the clock source selected by mask option.
6
uzzer output frequency selection. There are eight types of frequency signals for buzzer
output: Clock/2
~Clock/2
. Clock means the clock source selected by mask option.
7
Wake-up selection. This option defines the wake-up capability. External I/O pins (PA
only) all have the capability to wake-up the chip from a HALT by a falling edge.
8
Pull-high selection. This option is to decide whether the pull-high resistance is visible or
not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high)
9
PA0~PA3 and PC CMOS or NMOS selection.
The structure of PA0~PA3 and PC each 4 bits can be selected as CMOS or NMOS individ-
ually. When the CMOS is selected, the related pins only can be used for output opera-
tions. When the NMOS is selected, the related pins can be used for input or output
operations. (PA4~PA7 are always NMOS)