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參數(shù)資料
| 型號(hào)： | HT49C50 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 25/52頁 |
| 文件大?。?/td> | 318K |
| 代理商： | HT49C50 |
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HT49C50
25
August 18, 1999
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Input/output ports
Input/output ports
There are a 12-bit bidirectional input/output
port,an8-bitinputportintheHT49C50,labeled
PA, PB and PC which are mapped to [12H],
[14H] and [16H] of the RAM, respectively.
PA0~PA3 can be configured as CMOS (output)
or NMOS (input/output) with or without
pull-high resistor by mask option. PA4~PA7 are
alwayspull-highandNMOS(input/output).Ifyou
choose NMOS (input), each bit on the port
(PA0~PA7) can be configured as a wake-up input.
PBcanonlybeusedforinputoperation,andeach
bitontheportcanbeconfiguredwithpull-highre-
sistor. PC can be configured as CMOS output or
NMOSinput/outputwithorwithoutpull-highre-
sistorbymaskoption.Alltheportfortheinputop-
eration (PA, PB and PC), these ports are
non-latched,thatis,theinputsshouldbereadyat
theT2risingedgeoftheinstruction MOVA,[m]
(m=12Hor14H).ForPA,PCoutputoperation,all
data are latched and remain unchanged until the
outputlatch is rewritten.
When the PA and PC structures are open drain
NMOS type, it should be noted that, before
reading data from the pads, a 1 should be
written to the related bits to disable the NMOS
device. That is executing first the instruction
SET [m].i (i=0~7 for PA) to disable related
NMOS device, and then MOV A, [m] to get
stable data.
After chip reset, these input lines remain at the
high level or are left floating (by mask option).
Each bit of these output latches can be set or
cleared by the
SET [m].i
(m=12H or 16H) instructions.
and
CLR [m].i
Some instructions first input data and then fol-
low the output operations. For example, SET
[m].i , CLR [m].i , CPL[m] , CPLA[m] read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the ac-
cumulator.
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