![](http://datasheet.mmic.net.cn/390000/HT48R50A_datasheet_16811619/HT48R50A_19.png)
HT48R50A-1
Rev. 1.10
19
July 2, 2001
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are
implemented in the . The Timer/Event Counter
0 contains an 8-bit programmable count-up
counter and the clock may come from an exter-
nal source or from the system clock or RTC.
The Timer/Event Counter 1 contains an 16-bit
programmable count-up counter and the clock
may come from an external source or from the
system clock divided by 4 or RTC.
Using the internal clock sources, there are 2
reference time-bases for Timer/Event Counter
Label (TMR0C)
Bits
Function
PSC0~PSC2
0~2
To define the prescaler stages, PSC2, PSC1, PSC0=
000: f
INT
=f
SYS
/2 or f
RTC
/2
001: f
INT
=f
SYS
/4 or f
RTC
/4
010: f
INT
=f
SYS
/8 or f
RTC
/8
011: f
INT
=f
SYS
/16 or f
RTC
/16
100: f
INT
=f
SYS
/32 or f
RTC
/32
101: f
INT
=f
SYS
/64 or f
RTC
/64
110: f
INT
=f
SYS
/128 or f
RTC
/128
111: f
INT
=f
SYS
/256 or f
RTC
/256
TE
3
To define the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
5
Unused bit, read as"0"
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C register
Label (TMR1C)
Bits
Function
0~2
Unused bit, read as"0"
TE
3
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as"0"
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C register