HT48R30A-1
9
November 29, 2000
(INTC;0BH), Watchdog Timer option setting
register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H, PG;1EH) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H,
PGC;1FH). The remaining space before the
20H is reserved for future expanded usage and
reading these locations will get "00H". The
general purpose data memory, addressed from
20H to 7FH, is used for data and control infor-
mation under instruction commands.
All of the data memory areas can handle arith-
metic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer registers (MP).
Indirect addressing register
Location 00H is indirect addressing register
that is not physically implemented. Any
read/write operation of [00H] will access data
memory pointed to by MP. Reading location
00H itself indirectly will return the result 00H.
Writing indirectly results in no operation.
The memory pointer register (MP) is 8-bit reg-
isters.
Accumulator
The accumulator is closely related to ALU oper-
ations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
Arithmetic and logic unit
ALU
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following func-
tions:
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data op-
eration but also changes the status register.
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RAM mapping