HT48R30A-1
14
November 29, 2000
The port Awake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by ROM code op-
tion. Awakening from an I/O port stimulus, the
program will resume execution of the next in-
struction. If it awakens from an interrupt, two
sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
abledandthestackisnotfull,theregularinter-
rupt response takes place. If an interrupt
request flag is set to "1" before entering the
HALT mode, the wake-up function of the re-
lated interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system
clock period) to resume normal operation. In
other words, a dummy period will be inserted
after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual inter-
rupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
nextinstructionexecution,thiswillbeexecuted
immediately after the dummy period is fin-
ished.
To minimize power consumption, all the I/O
pins should be carefully managed before enter-
ing the HALT status. The RTC oscillator still
runs in the HALT mode (if the RTC oscillator is
enabled).
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The time-out during HALT is different from
other chip reset conditions, since it can perform
a "warm reset" that resets only the PC and SP,
leaving the other circuits in their original state.
Some registers remain unchanged during other
reset conditions. Most registers are reset to the
initialcondition whentheresetconditionsare
met. By examining the PD and TO flags, the
program can distinguish between different
"chip resets".
TO PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: "u" stands for "unchanged"
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-upTimer)providesanextra-delayof1024
system clock pulses when the system reset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
Reset circuit
!
' # ; !
, # " ' ' !
Reset timing chart