參數(shù)資料
型號(hào): HT48R30A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個(gè)I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 18/47頁
文件大?。?/td> 306K
代理商: HT48R30A-1
HT48R30A-1
18
November 29, 2000
There are 2 registers related to the timer/event
counter;TMR([0DH]),TMRC([0EH]).Twophys-
ical registers are mapped to TMR location; writ-
ing TMR makes the starting value be placed in
the timer/event counter preload register and
reading TMR gets the contents of the timer/event
counter. The TMRC is a timer/event counter con-
trol register, which defines some options.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which means the clock source comes
from an external (TMR) pin. The timer mode
functions as a normal timer with the clock
source coming from the f
INT
clock or RTC clock.
The pulse width measurement mode can be used
tocountthehighorlowleveldurationoftheexter-
nal signal. The counting is based on the f
INT
clock
or RTC clock.
In the event count or timer mode, once the
timer/event counter starts counting, it will count
from the current contents in the timer/event
counter to FFH. Once overflow occurs, the coun-
ter is reloaded from the timer/event counter
preload register and generates the interrupt re-
quest flag (TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with
the TON and TE bits equal to one, once the
TMR has received a transient from low to high
(or high to low if the TE bits is "0") it will start
counting until the TMR returns to the original
level and resets the TON. The measured result
will remain in the timer/event counter even if
the activated transient occurs again. In other
words, only one cycle measurement can be
done. Until setting the TON, the cycle measure-
ment will function again as long as it receives
further transient pulse. Note that, in this oper-
ating mode, the timer/event counter starts
counting not according to the logic level but ac-
cording to the transient edges. In the case of
counter overflows, the counter is reloaded from
the timer/event counter preload register and is-
sues the interrupt request just like the other
two modes. To enable the counting operation,
the timer ON bit (TON; bit 4 of TMRC) should
be set to 1. In the pulse width measurement
mode,theTONwillbeclearedautomaticallyaf-
ter the measurement cycle is completed. But in
the other two modes the TON can only be reset
by instructions. The overflow of the timer/event
counter 0/1 is one of the wake-up sources. No
matter what the operation mode is, writing a 0
to ETI can disable the corresponding interrupt
services.
In the case of timer/event counter OFF condi-
tion, writing data to the timer/event counter
preload register will also reload that data to
the timer/event counter. But if the timer/event
counter is turned on, data written to it will only
be kept in the timer/event counter preload reg-
ister. The timer/event counter will still operate
until overflow occurs (a timer/event counter re-
loading will occur at the same time). When the
timer/event counter (reading TMR) is read, the
clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this
mustbetakenintoconsiderationbytheprogram-
mer.
The bit0~bit2 of the TMRC can be used to de-
fine the pre-scaling stages of the internal clock
sources of timer/event counter. The definitions
are as shown. The overflow signal of
timer/event counter can be used to generate
PFD signals for buzzer driving.
Input/output ports
There are 25 bidirectional input/output lines in
the microcontroller, labeled from PA to PC and
PG, which are mapped to the data memory of
[12H], [14H], [16H] and [1EH] respectively. All of
these I/O ports can be used for input and output
operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at
the T2 rising edge of instruction "MOV A,[m]"
(m=12H, 14H, 16H or 1EH). For output opera-
tion, all the data is latched and remains un-
changed until the output latch is rewritten.
Each I/O line has its own control register (PAC,
PBC, PCC, PGC) to control the input/output
configuration. With this control register, CMOS
output or schmitt trigger input with or without
pull-high resistor structures can be reconfig-
ured dynamically (i.e. on-the-fly) under soft-
ware control. To function as an input, the
corresponding latch of the control register must
write "1". The input source also depends on the
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