參數(shù)資料
型號: HT48R12-18DIP-F-0
英文描述: IC-8-BIT MCU
中文描述: 集成電路8位微控制器
文件頁數(shù): 31/59頁
文件大?。?/td> 2625K
代理商: HT48R12-18DIP-F-0
Mnemonic
Description
F lag Affected
Instruction
Cycle
Miscellaneous
NOP
CLR [m]
SE T [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog timer
Pre-clear Watchdog timer
Pre-clear Watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
E nter power down mode
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
1
1
(1)
1
(1)
1
1
1
1
(1)
1
1
Notes: x: 8-bit immediate data
m: 7-bit data memory address for HT48C10/HT48C30
m: 8-bit data memory address for HT48C50/HT48C70
A: Accumulator
i: 0~7 number of bits
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
: Flag(s) is affected
–: Flag(s) is not affected
*: Flag(s) may be affected by the execution status
(1)
: If a loading to PCL register occurs, the execution cycle of the instructions will be delayed
one more cycle (4 system clocks).
(2)
: If a skip to next instruction occurs, the execution cycle of instructions will be delayed one
more cycle (4 system clocks). Otherwise the original execution cycles remain unchanged.
(3)
:
(1)
or
(2)
HT48CXX/HT48RXX
31
25th May ’99
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